Phase-change memory arrays are based upon memory elements that switch among two material phases, or gradations thereof, to exhibit corresponding distinct electrical characteristics. Alloys of elements of group VI of the periodic table, such as Te, S or Se, referred to as chalcogenides or chalcogenic materials, can be used advantageously in phase change memory cells. In the chalcogenides, the resistivity may vary by two or more orders of magnitude when the material passes from the amorphous (more resistive) phase to the crystalline (more conductive) phase, and vice versa. In the amorphous state, moreover, the resistivity depends to a marked extent upon the temperature.
A chalcogenide memory device may utilize the wide range of resistance values available for the material as the basis of memory operation. Each resistance value corresponds to a distinct structural state of the chalcogenide material and one or more of the states can be selected and used to define operation memory states. Chalcogenide materials exhibit a crystalline state, or phase, as well as an amorphous state, or phase.
Different structural states of a chalcogenide material differ with respect to the relative proportions of crystalline and amorphous phase in a given volume or region of chalcogenide material. The range of resistance values is generally bounded by a set state and a reset state of the chalcogenide material. By convention, the set state is a low resistance structural state whose electrical properties are primarily controlled by the crystalline portion of the chalcogenide material and the reset state is a high resistance structural state whose electrical properties are primarily controlled by the amorphous portion of the chalcogenide material.
Phase change may be induced by increasing the temperature locally. Below 150° C., both of the phases are stable. Above 200° C., nucleation of the crystallites occurs and, if the material is kept at the crystallization temperature for a sufficiently long time, the chalcogenide material undergoes a phase change and becomes crystalline. To bring the chalcogenide back to the amorphous state, the temperature of the material is raised above the melting temperature (approximately 600° C.) and then cooled rapidly, i.e. quenched rapidly. From the electrical standpoint, it is possible to reach the crystallization and melting temperatures by causing an adequate current to flow through the phase change memory material, by current flowing through the cell structure and contacts.
Each memory state of a chalcogenide memory material corresponds to a distinct resistance value range, and each memory resistance value signifies unique informational content. Operationally, the chalcogenide material can be programmed into a particular memory state by providing an electric current pulse of an appropriate amplitude and duration to transform the chalcogenide material into the structural state having the desired resistance. By controlling the amount of energy provided to the chalcogenide material, it is possible to control the relative proportions of crystalline and amorphous phase regions within a volume of the material and to thereby control the structural (and corresponding memory) state of the chalcogenide material to store information, using cell structures and programming means familiar to those reasonably skilled in the art. The resulting resistance may be achieved, if necessary, by repeated writes and reads in a binary search.
Each memory state can be programmed by providing the current pulse characteristics of the state and each state can be identified, or “read”, in a non-destructive fashion by measuring the resistance. Programming among the different states is reversible and the memory devices can be written many times despite limited endurance for write. Between writes, the bits may be read for a virtually unlimited number of read cycles that retrieve the stored data, even after loss of power that may occur periodically between write and read operations (“non-volatile memory” data retention without electrical power).
The variable resistance memory functionality of chalcogenide materials is currently being exploited in the in the phase change memory (PCM) devices that are beginning to appear on the market, also known as Ovonic Universal Memory Ovonic Unified Memory (OUM). Basic principles and operation of PCM type devices are presented, for example, in U.S. Pat. Nos. 6,859,390; 6,774,387; 6,687,153; and 6,314,014; the disclosures of which are incorporated by reference herein, as well as in several journal articles including, “Low Field Amorphous State Resistance and Threshold Voltage Drift in Chalcogenide Materials,” published in EE transactions on Electron Devices, vol. 51, p. 714-719 (2004) by Pirovana et al.; and “Morphing Memory,” published in IEEE Spectrum, vol. 167, p. 363-364 (2005) by Weiss.
The behavior (including switching, memory, and accumulation) and chemical compositions of chalcogenide materials have been described, for example, in the following U.S. Pat. Nos. 6,671,710; 6,714,954; 6,087,674; 5,166,758; 5,296,716; 5,536,947; 5,596,522; 5,825,046; 5,687,112; 5,912,839; and 3,530,441, the disclosures of which are hereby incorporated by reference. These references present proposed mechanisms that describe the behavior of chalcogenide materials. The references also describe the structural transformations from the crystalline state to the amorphous state (and vice versa) including a series of partially crystalline states in which the relative proportions of crystalline and amorphous regions may vary during the operation of electrical and optical chalcogenide materials.
Alternative chalcogenide alloy compositions have been investigated in an effort to further optimize the performance characteristics of chalcogenic devices. Chalcogenide materials or alloys may generally include a chalcogen element and one or more chemical or structural modifying elements. The chalcogen element (e.g. Te, Se, S) is selected from column VI of the periodic table and the modifying elements may be selected, for example, from column III (e.g. Ga, Al, In), column IV (e.g. Si, Ge, Sn), or column V (e.g. P, As, Sb) of the periodic table. Embodiments in accordance with the principles of the present invention may include binary, ternary, quaternary, and higher order chalcogenide alloys. Examples of chalcogenide materials are described in U.S. Pat. Nos. 5,166,758, 5,296,716, 5,414,271, 5,359,205, 5,341,328, 5,536,947, 5,534,712, 5,687,112, and 5,825,046 the disclosures of which are all incorporated by reference herein. Chalcogenide materials may also be the resultant of a reactive sputtering process: a chalcogenide nitride, or oxide, for example and chalcogenide may be modified by an ion implantation or other process.
Early work in chalcogenide devices demonstrated electrical switching behavior in which switching from an “off” resistive state to an “on” conductive state was induced upon application of a voltage at or above the threshold voltage of the active chalcogenide material. Adjusting the alloy so the material remains in the amorphous phase for this effect is the basis of the Ovonic Threshold Switch (OTS), a feature of chalcogenide materials. The OTS provides reproducible switching at fast switching speeds. Basic principles and operational features of the OTS are presented, for example, in U.S. Pat. Nos. 3,271,591; 5,543,737; 5,694,146; and 5,757,446; the disclosures of which are hereby incorporated by reference, as well as in several journal articles including “Reversible Electrical Switching Phenomena in Disordered Structures,” Physical Review Letters, vol. 21, p. 1450-1453 (1969) by S. R. Ovshinsky; “Amorphous Semiconductors for Switching, Memory, and Imaging Applications,” IEEE Transactions on Electron Devices, vol. ED-20, p. 91-105 (1973) by S. R. Ovshinsky and H. Fritzsche; which are hereby incorporated by reference. Three-terminal OTS devices are disclosed, for example, in U.S. Pats. No. 6,969,867 and 6,967,344; which are hereby incorporated by reference.
In many electronics applications, and particularly in integrated circuit applications, device size is an important parameter that has a direct impact on the cost/value/function of a device and the circuit of which it is a part. Any circuit or method that reduces the size of a device or devices required to accomplish a task is therefore highly desirable. One application area in which such a size reduction is particularly desirable is in the area of memory arrays, such as OUM memory arrays.